This application incorporates by reference Taiwanese application serial No. 89104206, filed on Mar. 8, 2000.
1. Field of the Invention
The invention relates in general to a method and system for testing integrated circuits (IC) and more particularly to a method and system for testing IC with test commands being received and outputted serially.
2. Description of the Related Art
The functionality of IC chips needs to be confirmed before the completion of its manufacturing. As such, the cost of testing an IC chip is regarded as an integral and major contributor to the overall cost of the chip and so, the less time it takes to complete the test, the less it will cost, and thus improve the competitiveness of the chip in the market. The testing of the IC chip is performed by a test machine which generates predefined test commands for the chip. The commands may either target specific functions in a collection of chips or a variety of functions in a specific chip. A test machine is regarded as an efficient one, thereby reducing the cost of the chip, if it detects several defective chips within a short period of time. The test commands and the following test results are conventionally transferred between the test machine and the chips in parallel input/output (PIO) manner. Thus, a number of pins on a chip are utilized to transfer the test commands and the test results. For instance, when 8-bit test commands are used in the testing of specific chips, eight pins on the chips will be used for transferring the test commands and the test results between the test machine and the chips.
The current trend in chip design is towards the integration of multiple functions into a single chip. However, the number of functions a single chip can handle is directly related to the number of functional pins on the chip. As mentioned before, the PIO method of testing IC chips requires the use of some pins of the chip. Before the advent of integrating several chips onto one, the number of pins of available for transferring commands and results in PIO manner were more than enough. Thus, the PIO method of testing is suitable for the individual chip. When individual chips are integrated into a single chip however, the number of available pins is decreased. If the number of pins that are available for testing purpose is smaller than the number of pins that are required to implement PIO, PIO method is not suitable for the integrated chip.
When the PIO test method is not applicable due to the lack of available pins, one solution is to apply pin-sharing to the chip design. When pin-sharing is applied to chip design, the pins of a chip become multifunctional (i.e. when operating in some situation, specific pins are used by a specific functional block. And in another situation, these pins are used by another functional block.) The major drawback of pin-sharing is that the design becomes complicated as the number of sharing pins is increased.
Since the number of pins on an IC chip is directly proportional to its size, a general trend nowadays is towards the minimization of the number of pins on a chip. This trend will obviously compound the issue of lack of pins and thus pin-sharing will become a serious problem.
It is therefore an object of the invention to provide a method and system for testing a chip with test commands transferred serially. According to the object of the invention, the testing system utilizes less number of pins for transferring test commands which will lessen the problem of complicated circuit design arising due to the use of the pin-sharing method.
According to the object of the invention, it provides a testing system in a chip, which is used for testing a circuit module of the chip. The testing system receives a reference clock and a test input signal outputted serially from a test machine. The testing system includes a serial/parallel converting circuit, a command port, a selector, a test data decoder, and a controlling circuit. The serial/parallel converting circuit is used for receiving the reference clock and the test input signal serially, producing a test command signal in parallel, and sending a test output signal to the test machine. The command port is used for receiving and storing the test command signal, and for outputting a first test signal and a second test signal. The selector is used for receiving the second test signal and producing a selection signal for selecting the circuit module of the chip. The test data decoder is used for receiving the first test signal, producing a test data signal as an input to the circuit module selected. The controlling circuit is used for outputting a controlling signal into the circuit module selected, wherein the circuit module produces the test output signal.
According to the object of the invention, it provides a testing system in a chip, which is used for testing a circuit module of the chip. The testing system receives a reference clock and a test input signal outputted from a test machine serially. The testing system includes a serial/parallel converting circuit, a command port, and a decoding/controlling circuit. The serial/parallel converting circuit is used for serially receiving the reference clock and the test input signal, producing a test command signal in parallel, and sending a test output signal to the test machine. The command port is used for storing and outputting the test command signal. The decoding/controlling circuit is used for receiving the test command signal, and producing a controlling signal and a test data signal, wherein the circuit module of the chip, in response to the controlling signal and the test data signal, produces the test output signal.
According to the object of the invention, it also provides a method of testing a chip, for testing at least one circuit module of the chip. The method includes the steps as follows. First, a test command is inputted serially. The test command is then decoded as a test data signal. Next, a test output signal is obtained after the circuit module to be tested receives the test data signal. Finally, the test output signal is outputted serially.
According to the object of the invention, it also provides a system of testing a chip, for testing a circuit module of the chip. The system is integrated into the chip and receives a reference clock and a test input signal from a test machine serially. The system includes a serial/parallel converting circuit, a command port, a decoder, and a state machine. The serial/parallel converting circuit is used for receiving the reference clock and the test input signal serially, producing a test command signal in parallel, and sending a test output signal to the test machine. The command port is used for receiving and storing the test command signal. The decoder is used for decoding the test command signal as a first decoded signal and a second decoded signal, wherein, in response to the first decoded signal, the circuit module produces an output signal. The state machine, in response to the second decoded signal and the output signal, produces the test output signal, which is sent to the test machine.